* /home/radhadk260501/esim-workspace/mixed_circuit_mux/mixed_circuit_mux.cir

* u4  net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ net-_u4-pad4_ radha_mux
* u5  i0 i1 sel net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ adc_bridge_3
* u6  net-_u4-pad4_ net-_r3-pad1_ dac_bridge_1
v1  i0 gnd pulse(0 5 1m 1m 1m 5 10)
v2  i1 gnd pulse(0 5 1m 1m 1m 2.5 5)
v3  sel gnd pulse(0 5 1m 1m 1m 10 20)
* u1  i0 plot_db
* u2  i1 plot_db
r3  net-_r3-pad1_ y 1k
c1  y gnd 1u
* u7  y plot_db
* u3  sel plot_db
a1 [net-_u4-pad1_ ] [net-_u4-pad2_ ] [net-_u4-pad3_ ] [net-_u4-pad4_ ] u4
a2 [i0 i1 sel ] [net-_u4-pad1_ net-_u4-pad2_ net-_u4-pad3_ ] u5
a3 [net-_u4-pad4_ ] [net-_r3-pad1_ ] u6
* Schematic Name:                             radha_mux, NgSpice Name: radha_mux
.model u4 radha_mux(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) 
* Schematic Name:                             adc_bridge_3, NgSpice Name: adc_bridge
.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
* Schematic Name:                             dac_bridge_1, NgSpice Name: dac_bridge
.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) 
.tran 1e-00 40e-00 0e-00

* Control Statements 
.control
run
print allv > plot_data_v.txt
print alli > plot_data_i.txt
plot db(i0)
plot db(i1)
plot db(y)
plot db(sel)
.endc
.end